The present invention relates generally to semiconductor package testing, and more particularly, to testing packaged semiconductor devices at the package level.
Defects introduced in the backend of the silicon manufacturing process can cause faulty parts to be unknowingly shipped to customers. These defects can include, but are not limited to, scratches on the surface of the wafer due to manual handling, and to defects introduced in the package assembly process itself. Scratches on the surface of the wafer can create shorts between power and ground straps. Defects in the package assembly process can include defects on the substrate and wire bond.
In order to reduce the number of latent defects of packaged semiconductor devices being shipped to the field, high voltage stress test (HVST) is an industry-wide technique to accelerate defects to failure by elevating power supplies above their specification. The focus of traditional HVST is on wafer fab defects that affect the integrity of gate oxide and contacts, for example. Often, this technique is used at wafer-level test, before the package assembly process. Accordingly, defects introduced after wafer-level test and during the assembly process will not be accelerated by traditional HVST.
Traditional HVST stresses only power pins with elevated voltage. Traditional continuity and leakage electrical testing groups inputs/outputs into two groups that are stressed in parallel, i.e. evens and odds. This is done to reduce test time, but it leaves open a potential hole in coverage for complex packages, ball grid arrays for example, which even and odd groupings do not adequately address.
It is therefore desirable to provide a cost effective method for accelerating defects introduced during the assembly process on any input/output, power or ground pin, and to screen for defects during package-level test.